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APCSAC
2001
IEEE

Retargetable Cache Simulation Using High Level Processor Models

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Retargetable Cache Simulation Using High Level Processor Models
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simulator. The cache simulator has been implemented using a retargetable instruction set simulator from the SimnML [9] processor description language. The retargetability helps in cache simulation and evaluation much before the actual processor design.
Rajiv A. Ravindran, Rajat Moona
Added 23 Aug 2010
Updated 23 Aug 2010
Type Conference
Year 2001
Where APCSAC
Authors Rajiv A. Ravindran, Rajat Moona
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