70 search results - page 1 / 14 » Retargetable Cache Simulation Using High Level Processor Mod... |
APCSAC
2001
IEEE
13 years 8 months ago
2001
IEEE
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
RSP
2000
IEEE
13 years 8 months ago
2000
IEEE
This paper describes a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators, compilers etc., using processor models in a ge...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
We present a framework for rapidly exploring the design space of low power application-specific programmable processors (ASPP), in particular mediaprocessors. We focus on a catego...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
ANSS
2004
IEEE
13 years 8 months ago
2004
IEEE
To enable optimizations in memory access behavior of high performance applications, cache monitoring is a crucial process. Simulation of cache hardware is needed in order to allow...