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DAC
1996
ACM

RTL Emulation: The Next Leap in System Verification

13 years 8 months ago
RTL Emulation: The Next Leap in System Verification
ion. Production use of text-based methodology has enabled designers to capture designs of hundreds of thousands of gates using graphic ESDA tools. Source: Data Quest (Verilog/VHDL Market SpecialReport) Second, is the change in manufacturing process. Today, designers are using 0.35 micron or even 0.25 micron technology. Submicron manufacturing capabilities enable millions of gates on a single chip. Sematech predicts that 0.25 micron technology will be ubiquitous by 1998 and the average chip complexity will be 20 million transistors. With most ASIC fabs running 0.5 micron processes reliably, and several delivering or scheduling a move to 0.25 micron soon, manufacturing capabilities are quickly outgrowing the capacity of current design tools. The obstacles in developing new generation of electronics revolve around three key questions:
Sanjay Sawant, Paul Giordano
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1996
Where DAC
Authors Sanjay Sawant, Paul Giordano
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