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DAC
1996
ACM
9 years 3 months ago
VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems
This paper presents a new concept for accurate modeling and timing simulationof electronicsystems integrated in a typical VHDL design environment, taking into account the requirem...
Bernhard Wunder, Gunther Lehmann, Klaus D. Mü...
DAC
1996
ACM
9 years 3 months ago
Opportunities and Obstacles in Low-Power System-Level CAD
A case study in low-power system-level design is presented. We detail the design of a low-power embedded system, a touchscreen interface device for a personal computer. This devic...
Andrew Wolfe
DAC
1996
ACM
9 years 3 months ago
Efficient Communication in a Design Environment
This paper presents a new communication service. The novelty of the work resides in the distributed architecture adopted which is based on communication agents in every tool and i...
Idalina Videira, Paulo Veríssimo, Helena Sa...
DAC
1996
ACM
9 years 3 months ago
Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems
-- This paper presents an efficient method for the timing verification of concurrent systems, modeled as labeled Timed Petri nets. The verification problems we consider require us ...
Eric Verlind, Gjalt G. de Jong, Bill Lin
DAC
1996
ACM
9 years 3 months ago
Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications
Deep sub-micron processing technologies have enabled the implementation of new application-specificembeddedarchitecturesthat integrate multiple software programmable processors (e...
Steven Vercauteren, Bill Lin, Hugo De Man
DAC
1996
ACM
9 years 3 months ago
Improving the Efficiency of Power Simulators by Input Vector Compaction
Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern dependent. To obtain an accurate power estimate, a large input...
Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, ...
DAC
1996
ACM
9 years 3 months ago
Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems
In this paper we present an integrated simulation paradigm in which parallel mixed-mode co-simulation is accomplished by integrating sequential simulators in a software simulation ...
Antonio R. W. Todesco, Teresa H. Y. Meng
DAC
1996
ACM
9 years 3 months ago
Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic
-- We present a new heuristic algorithm for hazard-free minimization of two-level logic. On nearly all examples, the algorithm finds an exactly minimum-cost cover. It also solves s...
Michael Theobald, Steven M. Nowick, Tao Wu
DAC
1996
ACM
9 years 3 months ago
Delay Minimal Decomposition of Multiplexers in Technology Mapping
Technology mapping requires the unmapped logic network to be represented in terms of base functions, usually two-input NORs and inverters. Technology decomposition is the step tha...
Shashidhar Thakur, D. F. Wong, Shankar Krishnamoor...
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