Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems

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We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa

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Abstract Graph Representation | DATE 1998 | Hardware | Target Architectures | Worst Case Delay |

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Added	04 Aug 2010
Updated	04 Aug 2010
Type	Conference
Year	1998
Where	DATE
Authors	Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop

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Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems

Abstract Graph Representation | DATE 1998 | Hardware | Target Architectures | Worst Case Delay |

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