DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
After write operations, BIST schemes for RAMs relying on signature analysis must compress the entire memory contents to update the reference signature. This paper introduces a new...
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
In this paper, we present an approach to synthesize multiple behavior modules. Given n DFGs to be implemented, the previous methods scheduled each of them sequentially, and implem...
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
This paper presents a VLSI Architecture to implement the forward and inverse 2-D Discrete Wavelet Transform (FDWT/IDWT), to compress medical images for storage and retrieval. Loss...
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
Efficient dc fault simulation of nonlinear analog circuits is addressed in this paper. Two techniques, one-step relaxation and adaptive simulation continuation, are proposed. By on...
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
Simple disjunctive decomposition is a special case of logic function decompositions, where variables are divided into two disjoint sets and there is only one newly introduced vari...
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at...
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...