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DATE
1999
IEEE

At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks

9 years 4 months ago
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks
As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-defined register is proposed. Test methods based on the new architecture can accomplish cost-effective at-speed testing and propagation delay measurements on boardlevel interconnects. Particularly when the board under test has multiple domains of interconnects controlled by different clock speeds, our at-speed solution is much more efficient than other previous works.
Jongchul Shin, Hyunjin Kim, Sungho Kang
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where DATE
Authors Jongchul Shin, Hyunjin Kim, Sungho Kang
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