Statistical path selection for at-speed test

Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a traditional fault model. Due to parametric variations, different paths can be critical in different parts of the process space, and the union of such paths must be tested to obtain good process space coverage. This paper proposes a novel branch-and-bound algorithm that elegantly and efficiently solves the hitherto open problem of statistical path tracing. The resulting paths are used for at-speed structural testing. A new Test Quality Metric (TQM) is proposed and paths which maximize this metric are selected. After chip timing has been performed, the path selection procedure is extremely efficient. Path selection for a multi-million gate chip design can be completed in a matter of seconds.

• Type: Conference
• Year: 2008
• Where: ICCAD
• Authors: Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chandu Visweswariah
• Keywords: Hardware, ICCAD 2008, Multi-million Gate Chip, Path Selection Procedure, Subtle Delay Changes