System-Level Modeling of Dynamically Reconfigurable Co-processors

Dynamically reconfigurable co-processors (DRCs) are interesting design alternatives when both flexibility and performance are concerns. However, it is difficult to study the performance impact of including such devices into design when using traditional design methods and tools. In this paper, we present easily adaptable system-level techniques, which are able to perform fast exploration of different reconfiguration alternatives. A SystemCbased modeling method for DRCs and a high-level synthesis-based estimation tool to support system partitioning are presented.

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Yang Qu, Kari Tiensyrjä, Kostas Masselos
• Keywords: Adaptable System-level Techniques, FPL 2004, Interesting Design Alternatives, Traditional Design Methods