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DATE
2007
IEEE
97views Hardware» more  DATE 2007»
14 years 3 months ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine...
DATE
2003
IEEE
151views Hardware» more  DATE 2003»
14 years 2 months ago
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
Adrijean Andriahantenaina, Hervé Charlery, ...
RTAS
1997
IEEE
14 years 1 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
AOSE
2005
Springer
14 years 2 months ago
Using the Analytic Hierarchy Process for Evaluating Multi-Agent System Architecture Candidates
Abstract. Although much effort has been spent on suggesting and implementing new architectures of Multi-Agent Systems (MAS), the evaluation and comparison of these has often been d...
Paul Davidsson, Stefan J. Johansson, Mikael Svahnb...
SENSYS
2005
ACM
14 years 2 months ago
Design and deployment of industrial sensor networks: experiences from a semiconductor plant and the north sea
Sensing technology is a cornerstone for many industrial applications. Manufacturing plants and engineering facilities, such as shipboard engine rooms, require sensors to ensure pr...
Lakshman Krishnamurthy, Robert Adler, Philip Buona...