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2010
Springer

Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures

9 years 8 months ago
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures
Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on the same architecture. This paper investigates systolic mapping techniques for mapping biosignal processing algorithms to CGRA architectures. A novel methodology using synchronous data flow (SDF) graphs and control and data flow (CDF) graphs for mapping is presented. Mapping signal processing algorithms in this manner is shown to give up to a 88% reduction in memory accesses and significant savings in fetch and decode operations while providing high throughput.
Kunjan Patel, Chris J. Bleakley
Added 02 Sep 2010
Updated 02 Sep 2010
Type Conference
Year 2010
Where ARC
Authors Kunjan Patel, Chris J. Bleakley
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