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ARVLSI
1995
IEEE

A technique for high-speed, fine-resolution pattern generation and its CMOS implementation

9 years 11 months ago
A technique for high-speed, fine-resolution pattern generation and its CMOS implementation
This paper presents an architecture for generating a high-speed data pattern with precise edge placement resolution by using the matched delay technique. The technique involves passing clock and data signals through arrays of matched delay elements in such a way that the data rate and resolution of the generated data stream are controlled by the di erence of these matched delays. This di erence can be made much smaller than an absolute gate delay. Since the resolution of conventional designs is determined by these absolute delays, the matched delay technique yields a much ner resolution than traditional methods and, in addition, generates high data rate patterns without the need of a high-speed clock. The matched delay technique lends itself to high-precision and high-speed applications such as fast network interfaces or test pattern generators. This paper also describes a matched
Gary C. Moyer, Mark Clements, Wentai Liu, Toby Sch
Added 25 Aug 2010
Updated 25 Aug 2010
Type Conference
Year 1995
Where ARVLSI
Authors Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III
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