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ISVLSI
2008
IEEE

Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations

9 years 4 months ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. In this paper, we consider the placement of standard cells and gate arrays (modules) under thermal considerations. Our contributions include: (i) an algorithm for optimal placement of the gates or cells to minimize the possible occurrence of hot spots, (ii) results of sensitivity analysis of thermal characteristic of a layout with respect to the power densities of the modules in the layout, and identifying three classes of modules, and (iii) an algorithm for optimal placement of modules, with minimum possible occurrence of hot spots, and reasonable estimated interconnect lengths. Experimental results on randomly generated and standard benchmark instances are quite encouraging.
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa
Added 31 May 2010
Updated 31 May 2010
Type Conference
Year 2008
Where ISVLSI
Authors Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta
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