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2007
IEEE

Three-dimensional multiprocessor system-on-chip thermal optimization

9 years 10 months ago
Three-dimensional multiprocessor system-on-chip thermal optimization
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density of 3D MPSoCs increases with the number of active layers, resulting in high chip temperatures. This can reduce system reliability, reduce performance, and increase cooling cost. Thermal optimization for 3D MPSoCs imposes numerous challenges. It is difficult to manage assignment and scheduling of heterogeneous workloads to maintain thermal safety. In addition, the thermal characteristics of 3D MPSoCs differ from those of 2D MPSoCs because each stacked layer has a different thermal resistance to the ambient and verticallyadjacent processors have strong temperature correlation. We propose a 3D MPSoC thermal optimization algorithm that conducts task assignment, scheduling, and voltage scaling. A power balancing algorithm is initially used to distribute tasks among cores and active layers. Detailed thermal analys...
Chong Sun, Li Shang, Robert P. Dick
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where CODES
Authors Chong Sun, Li Shang, Robert P. Dick
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