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2010
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Trace signal selection to enhance timing and logic visibility in post-silicon validation

9 years 9 months ago
Trace signal selection to enhance timing and logic visibility in post-silicon validation
Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window, which is used to analyze logic errors during post-silicon validation. Due to limitation in the bandwidth of trace buffers, only few state elements can be selected for tracing. In this work we first propose two improvements to existing "signal selection" algorithms to further increase the logic restorability inside the chip. In addition, we observe that different selections of trace signals can result in the same quality, measured as a logic visibility metric. Based on this observation, we propose a procedure which biases the selection to increase the restorability of a desired set of critical state elements, without sacrificing the (overall) logic visibility. We propose to select the critical state elements to increase the "timing visibility" inside the chip to facilitate the debugging of timing errors which are perhaps the most challengin...
Hamid Shojaei, Azadeh Davoodi
Added 11 Feb 2011
Updated 11 Feb 2011
Type Journal
Year 2010
Where ICCAD
Authors Hamid Shojaei, Azadeh Davoodi
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