Using Decision Diagrams to Design ULMs for FPGAs

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Using Decision Diagrams to Design ULMs for FPGAs
—Many modern Field Programmable Logic Arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs. Such blocks, known as Universal Logic Modules (ULMs), have already been considered for application in FPGAs; in this paper, we propose a new class of ULMs which is more useful in the FPGA environment. Methodology for systematic development of such blocks is presented, based on the BDD description of logic functions. We give an explicit construction of a three-input LUT replacement that requires only five programming bits, which is the optimum for such ULMs. A realistic size four-input LUT replacement is obtained which uses 13 programming bits.
Zeljko Zilic, Zvonko G. Vranesic
Added 23 Dec 2010
Updated 23 Dec 2010
Type Journal
Year 1998
Where TC
Authors Zeljko Zilic, Zvonko G. Vranesic
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