Sciweavers

Share
SIES
2010
IEEE

Verification of a CAN bus model in SystemC with functional coverage

8 years 3 months ago
Verification of a CAN bus model in SystemC with functional coverage
Abstract--Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which is a challenging task for the verification engineer. To cope with complexity, verification techniques working on different ion levels are best practice. SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification. However, SCV has several drawbacks such as lack of functional coverage. In this paper we present a functional coverage library that implements parts of the IEEE 1800-2005 SystemVerilog standard and allows capturing functional coverage throughout the design and verification process with SystemC. Moreover, we will demonstrate the usability of the approach with a case study working on a...
Christoph Kuznik, Gilles B. Defo, Wolfgang Mü
Added 15 Feb 2011
Updated 15 Feb 2011
Type Journal
Year 2010
Where SIES
Authors Christoph Kuznik, Gilles B. Defo, Wolfgang Müller 0003
Comments (0)
books