Sciweavers

Share
FPL
2000
Springer

Verification of Dynamically Reconfigurable Logic

10 years 6 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the...
David Robinson, Patrick Lysaght
Added 24 Aug 2010
Updated 24 Aug 2010
Type Conference
Year 2000
Where FPL
Authors David Robinson, Patrick Lysaght
Comments (0)
books