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FMCAD
2004
Springer
13 years 9 months ago
Memory Efficient All-Solutions SAT Solver and Its Application for Reachability Analysis
This work presents a memory-efficient All-SAT engine which, given a propositional formula over sets of important and non-important variables, returns the set of all the assignments...
Orna Grumberg, Assaf Schuster, Avi Yadgar
FMCAD
2004
Springer
13 years 11 months ago
Increasing the Robustness of Bounded Model Checking by Computing Lower Bounds on the Reachable States
Most symbolic model checkers are based on either Binary Decision Diagrams (BDDs), which may grow exponentially large, or Satisfiability (SAT) solvers, whose time requirements rapi...
Mohammad Awedh, Fabio Somenzi
FMCAD
2004
Springer
13 years 11 months ago
Simple Bounded LTL Model Checking
We present a new and very simple translation of the bounded model checking problem which is linear both in the size of the formula and the length of the bound. The resulting CNF-fo...
Timo Latvala, Armin Biere, Keijo Heljanko, Tommi A...
FMCAD
2004
Springer
13 years 9 months ago
Bloom Filters in Probabilistic Verification
Abstract. Probabilistic techniques for verification of finite-state transition systems offer huge memory savings over deterministic techniques. The two leading probabilistic scheme...
Peter C. Dillinger, Panagiotis Manolios
FMCAD
2004
Springer
13 years 9 months ago
Verification of Analog and Mixed-Signal Circuits Using Hybrid System Techniques
In this paper we demonstrate a potential extension of formal verification methodology in order to deal with time-domain properties of analog and mixed-signal circuits whose dynamic...
Thao Dang, Alexandre Donzé, Oded Maler
Formal Methods
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