54 search results - page 11 / 11 » A Bus Delay Reduction Technique Considering Crosstalk |
FPL
2003
Springer
13 years 10 months ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
INFOCOM
1999
IEEE
13 years 9 months ago
1999
IEEE
We consider designing near video on demand (VoD) systems that minimize start-up latency while maintaining high image quality. Recently several research teams have developed period...
ASAP
2005
IEEE
13 years 10 months ago
2005
IEEE
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...