54 search results - page 3 / 11 » A Bus Delay Reduction Technique Considering Crosstalk |
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
Inductance effects of on-chip interconnects have become more and more significant in today’s high-speed digital circuits, especially for global interconnects such as signal buse...
IOLTS
2003
IEEE
13 years 11 months ago
2003
IEEE
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies....
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
—The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. Howeve...