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EUROPAR
2009
Springer
13 years 11 months ago
A Case Study of Communication Optimizations on 3D Mesh Interconnects
Optimal network performance is critical to efficient parallel scaling for communication-bound applications on large machines. With wormhole routing, no-load latencies do not increa...
Abhinav Bhatele, Eric J. Bohm, Laxmikant V. Kal&ea...
SLIP
2009
ACM
13 years 11 months ago
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
13 years 2 months ago
Power distribution paths in 3-D ICS
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
Vasilis F. Pavlidis, Giovanni De Micheli
ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...
COMPUTING
2008
174views more  COMPUTING 2008»
13 years 5 months ago
Multilevel algorithms for Rannacher-Turek finite element approximation of 3D elliptic problems
Generalizing the approach of a previous work [15] the authors present multilevel preconditioners for three-dimensional (3D) elliptic problems discretized by a family of Rannacher ...
Ivan Georgiev, Johannes Kraus, Svetozar Margenov