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» A Compact Transactional Memory Multiprocessor System on FPGA
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FPL
2008
Springer
138views Hardware» more  FPL 2008»
13 years 7 months ago
An efficient run-time router for connecting modules in FPGAS
It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents ...
Jorge Surís, Cameron Patterson, Peter Athan...
FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
13 years 12 months ago
A practical FPGA-based framework for novel CMP research
Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...
Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy T...
HOTOS
2007
IEEE
13 years 9 months ago
Is the Optimism in Optimistic Concurrency Warranted?
Optimistic synchronization allows concurrent execution of critical sections while performing dynamic conflict detection and recovery. Optimistic synchronization will increase perf...
Donald E. Porter, Owen S. Hofmann, Emmett Witchel
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
13 years 10 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
LCTRTS
2010
Springer
14 years 19 days ago
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
Ines Viskic, Lochi Lo Chi Yu Lo, Daniel Gajski