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CF
2007
ACM
13 years 9 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
IPPS
1998
IEEE
13 years 9 months ago
Virtual FPGAs: Some Steps Behind the Physical Barriers
Recent advances in FPGA technologies allow to configure the RAM-based FPGA devices in a reduced time as an effective support for real-time applications. The physical dimensions of ...
William Fornaciari, Vincenzo Piuri
IPPS
2006
IEEE
13 years 11 months ago
A multiprocessor architecture for the massively parallel model GCA
The GCA (Global Cellular Automata) model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical...
Wolfgang Heenes, Rolf Hoffmann, Johannes Jendrsczo...
ICCS
2009
Springer
13 years 12 months ago
A Massively Parallel Architecture for Bioinformatics
Abstract. Today’s general purpose computers lack in meeting the requirements on computing performance for standard applications in bioinformatics like DNA sequence alignment, err...
Gerd Pfeiffer, Stefan Baumgart, Jan Schröder,...
IPPS
2003
IEEE
13 years 10 months ago
Architectural Frameworks for MPP Systems on a Chip
Advances in fabrication techniques are now enabling new hybrid CPU/FPGA computing resources to be integrated onto a single chip. While these new hybrids promise significant perfor...
David L. Andrews, Douglas Niehaus