4 search results - page 1 / 1 » A DFT Technique for Low Frequency Delay Fault Testing in Hig... |
ITC
2002
IEEE
13 years 9 months ago
2002
IEEE
DAC
1994
ACM
13 years 9 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
JCP
2006
13 years 4 months ago
2006
Abstract-- In this paper a novel pulse sequence testing methodology is presented [22] as an alternative to Time Domain Reflectometry (TDR) for transmission line health condition mo...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...