46 search results - page 1 / 10 » A Data Cache with Multiple Caching Strategies Tuned to Diffe... |
ICS
1995
Tsinghua U.
13 years 8 months ago
1995
Tsinghua U.
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
NAA
2004
Springer
13 years 10 months ago
2004
Springer
In this paper, we develop a probabilistic model for estimation of the numbers of cache misses during the sparse matrix-vector multiplication (for both general and symmetric matrice...
PCI
2005
Springer
13 years 10 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
15
Voted
IPPS
2010
IEEE
13 years 2 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...