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GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
13 years 9 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
AIM
2006
13 years 6 months ago
Observing the use of BPM tools: A step towards flexibility
: The development of the tools of Business Process Management (BPM) arises from the spread of the notion of process in the management universe. The application of BPM to strategic ...
Joseph Heili, Jean-Mathias Heraud, Laure France
BMCBI
2005
143views more  BMCBI 2005»
13 years 5 months ago
Gene capture prediction and overlap estimation in EST sequencing from one or multiple libraries
Background: In expressed sequence tag (EST) sequencing, we are often interested in how many genes we can capture in an EST sample of a targeted size. This information provides ins...
Ji-Ping Z. Wang, Bruce G. Lindsay 0002, Liying Cui...