Probabilistic maximum error modeling for unreliable logic circuits

9 years 1 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate failures due to the underlying device variabilities. Many of these failures would be transient in nature, necessitating the need for probabilistic logic based analysis. Current research in this area is concerned with computing error bounds, but they do not account for circuits structures or are usually derived for specific logic gate types. In addition, the usual focus is on computing the average error behavior. In this work, we propose an exact probabilistic error model to compute the maximum error in a circuit-specific manner and can handle various types of logical components in the same circuit. We model the error estimation problem as a maximum a posteriori estimate (MAP) over the joint error probability function of the entire circuit. Using this model, we can not only compute the maximum error, but can al...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
Added 16 Aug 2010
Updated 16 Aug 2010
Type Conference
Year 2007
Authors Karthikeyan Lingasubramanian, Sanjukta Bhanja
Comments (0)