81 search results - page 1 / 17 » A Design Methodology for Hardware Acceleration of Adaptive F... |
ASAP
2006
IEEE
13 years 11 months ago
2006
IEEE
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a stat...
VIS
2004
IEEE
14 years 6 months ago
2004
IEEE
We present a hardware-accelerated adaptive EWA volume splatting algorithm. EWA splatting combines a Gaussian reconstruction kernel with a low-pass image filter for high image qual...
ICIP
2000
IEEE
14 years 6 months ago
2000
IEEE
This paper describes an algorithm to implement image filtering and enhancement operations by processing adaptive triangular meshes that represent gray-level images. Experimental r...
FCCM
2005
IEEE
13 years 10 months ago
2005
IEEE
In many image processing applications, fast convolution of an image with a large 2D filter is required. Field Programable Gate Arrays (FPGAs) are often used to achieve this goal ...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
Abstract— In many image processing applications, fast convolution of an image with a large 2D filter is required. Field Programable Gate Arrays (FPGAs) are often used to achieve...