Sciweavers

81 search results - page 3 / 17
» A Design Methodology for Hardware Acceleration of Adaptive F...
Sort
View
DATE
2009
IEEE
159views Hardware» more  DATE 2009»
14 years 16 days ago
Design and implementation of a database filter for BLAST acceleration
— BLAST is a very popular Computational Biology algorithm. Since it is computationally expensive it is a natural target for acceleration research, and many reconfigurable archite...
Panagiotis Afratis, Constantinos Galanakis, Euripi...
VLSID
2002
IEEE
126views VLSI» more  VLSID 2002»
14 years 6 months ago
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication
With the projected significant growth in mobile internet and multimedia services, there is a strong demand for nextgeneration appliances capable of wireless image communication. O...
Debashis Panigrahi, Clark N. Taylor, Sujit Dey
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
13 years 12 months ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
IPPS
2007
IEEE
14 years 2 days ago
Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
Colin J. Ihrig, Justin Stander, Alex K. Jones
DPHOTO
2009
154views Hardware» more  DPHOTO 2009»
13 years 3 months ago
Optimal color filter array design: quantitative conditions and an efficient search procedure
Most digital cameras employ a spatial subsampling process, implemented as a color filter array (CFA), to capture color images. The choice of CFA patterns has a great impact on the...
Yue M. Lu, Martin Vetterli