116 search results - page 3 / 24 » A Framework for Parallelizing Load Stores on Embedded Proces... |
ICCAD
2001
IEEE
14 years 3 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
ET
2002
13 years 6 months ago
2002
Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a prog...
HPCA
2006
IEEE
14 years 6 months ago
2006
IEEE
Allowing loads to issue out-of-order with respect to earlier unresolved store addresses is very important for extracting parallelism in large-window superscalar processors. Blindl...
IEEEPACT
2002
IEEE
13 years 11 months ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...