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» A Framework for Scheduler Synthesis
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DATE
2003
IEEE
137views Hardware» more  DATE 2003»
13 years 11 months ago
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
We present two novel strategies to increase the scope for application of speculative code motions: (1) Adding scheduling steps dynamically during scheduling to conditional branche...
Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexa...
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
13 years 10 months ago
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Ni...
DAC
2002
ACM
14 years 6 months ago
Software synthesis from synchronous specifications using logic simulation techniques
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
Yunjian Jiang, Robert K. Brayton
EMSOFT
2001
Springer
13 years 10 months ago
Compiler Optimizations for Adaptive EPIC Processors
Abstract. Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting...
Krishna V. Palem, Surendranath Talla, Weng-Fai Won...
ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 2 months ago
Hardware synthesis from guarded atomic actions with performance specifications
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...
Daniel L. Rosenband