In reconfigurable systems, reconfiguration latency is a very important factor impact the system performance. In this paper, a framework is proposed that integrates the temporal pa...
Farhad Mehdipour, Morteza Saheb Zamani, H. R. Ahma...
In this paper, we describe a prototype software framework that implements a formalized methodology for partitioning computational intensive applications between reconfigurable har...
Michalis D. Galanis, Athanasios Milidonis, George ...
Advances in FPGA-based reconfigurable computers have made them a viable computing platform for a vast variety of computation demanding areas such as bioinformatics, speech recogni...
This paper presents a new design methodology able to bridge the gap between an abstract specification and a heterogeneous recone architecture. The EPICURE contribution is the resu...
Jean-Philippe Diguet, Guy Gogniat, Jean Luc Philip...
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...