This paper presents a formal model and a systematic approach to the validation of communication tures at a high level of abstraction. This model is described mathematically by a fu...
Abstract. We report on a case study in applying different formal methods to model and verify an architecture for administrating digital signatures. The architecture comprises seve...
David A. Basin, Hironobu Kuruma, Kunihiko Miyazaki...
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...
Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharide...
We present our experiences with the formal verification of an automotive chip used to control the safety features in a car. We used a BDD based model checker in our work. We descr...
Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl P...