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» A Genetic Testing Framework for Digital Integrated Circuits
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VLSID
1998
IEEE
116views VLSI» more  VLSID 1998»
13 years 9 months ago
Synthesis of Testable RTL Designs
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
SLIP
2005
ACM
13 years 11 months ago
Multilevel full-chip routing with testability and yield enhancement
We propose in this paper a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two ...
Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang...
ICDT
2010
ACM
211views Database» more  ICDT 2010»
14 years 2 months ago
Probabilistic Data Exchange
The work reported here lays the foundations of data exchange in the presence of probabilistic data. This requires rethinking the very basic concepts of traditional data exchange, ...
Ronald Fagin, Benny Kimelfeld, Phokion Kolaitis
WACV
2007
IEEE
13 years 11 months ago
Warped Document Image Restoration Using Shape-from-Shading and Physically-Based Modeling
With the pervasive use of handheld digital devices such as camera phones and PDAs, people have started to capture images as a way of recording information. However, due to the non...
Li Zhang, Chew Lim Tan
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
13 years 11 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock