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» A Genetic Testing Framework for Digital Integrated Circuits
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ITC
2000
IEEE
80views Hardware» more  ITC 2000»
13 years 10 months ago
A stand-alone integrated test core for time and frequency domain measurements
An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstructi...
Mohamed Hafed, Nazmy Abaskharoun, Gordon W. Robert...
GECCO
2006
Springer
143views Optimization» more  GECCO 2006»
13 years 9 months ago
A hybridized genetic parallel programming based logic circuit synthesizer
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system in...
Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung
WCE
2007
13 years 7 months ago
A Graph-based Framework for High-level Test Synthesis
Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniq...
Ali Pourghaffari bashari, Saadat Pourmozafari
EH
2003
IEEE
117views Hardware» more  EH 2003»
13 years 11 months ago
The Evolutionary Design and Synthesis of Non-Linear Digital VLSI Systems
This paper describes a multi-objective Evolutionary Algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a no...
Robert Thomson, Tughrul Arslan
ICES
2000
Springer
140views Hardware» more  ICES 2000»
13 years 9 months ago
Evolving Cellular Automata for Self-Testing Hardware
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...