29 search results - page 2 / 6 » A Graph Based Framework to Detect Optimal Memory Layouts for... |
IEEEPACT
2009
IEEE
13 years 2 months ago
2009
IEEE
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
VLSID
2008
IEEE
14 years 5 months ago
2008
IEEE
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
LCPC
1998
Springer
1998
Springer
A Loop Transformation Algorithm Based on Explicit Data Layout Representation for Optimizing Locality
13 years 9 months ago
We present a cache locality optimization technique that can optimize a loop nest even if the arrays referenced have different layouts in memory. Such a capability is required for a...
PLDI
2005
ACM
13 years 10 months ago
2005
ACM
This paper describes Automatic Pool Allocation, a transformation framework that segregates distinct instances of heap-based data structures into seperate memory pools and allows h...
IEEEPACT
1998
IEEE
13 years 9 months ago
1998
IEEE
Global locality analysis is a technique for improving the cache performance of a sequence of loop nests through a combination of loop and data layout optimizations. Pure loop tran...