7 search results - page 1 / 2 » A High-Performance Asynchronous FPGA: Test Results |
FCCM
2005
IEEE
13 years 10 months ago
2005
IEEE
We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC’s 0.18μm CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic ...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
ERSA
2006
13 years 6 months ago
2006
In this case study, various ways to partition a code between the microprocessor and FPGA are examined. Discrete image convolution operation with separable kernel is used as the ca...
FPGA
2010
ACM
13 years 2 months ago
2010
ACM
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
IWANN
2005
Springer
13 years 10 months ago
2005
Springer
In this paper, a fully functional prototype of an asynchronous 4-to-4 Address Event Representation (AER) mapper is presented. AER is an event driven communication protocol original...