19 search results - page 2 / 4 » A Large, Fast Instruction Window for Tolerating Cache Misses |
IPPS
2005
IEEE
13 years 10 months ago
2005
IEEE
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
ISCA
2005
IEEE
13 years 10 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
ASPLOS
2004
ACM
13 years 10 months ago
2004
ACM
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
MICRO
1998
IEEE
13 years 9 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
A dynamic optimizer is a runtime software system that groups a program’s instruction sequences into traces, optimizes those traces, stores the optimized traces in a softwarebase...