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SBCCI
2006
ACM
126views VLSI» more  SBCCI 2006»
13 years 11 months ago
Power constrained design optimization of analog circuits based on physical gm/ID characteristics
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
Alessandro Girardi, Sergio Bampi
DAC
2009
ACM
14 years 6 months ago
Thermal-driven analog placement considering device matching
With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the ther...
Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-...
DAC
2004
ACM
14 years 6 months ago
ORACLE: optimization with recourse of analog circuits including layout extraction
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...
Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd
DAC
2000
ACM
13 years 9 months ago
An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component m
Abstract: This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circ...
Carlo Guardiani, Sharad Saxena, Patrick McNamara, ...
DAC
2004
ACM
14 years 6 months ago
Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs
The negative effect of electromigration on signal and power line lifetime and functional reliability is an increasingly important problem for the physical design of integrated cir...
Goeran Jerke, Jürgen Scheible, Jens Lienig