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» A Layout-Aware Synthesis Methodology for RF Circuits
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ICCAD
2001
IEEE
106views Hardware» more  ICCAD 2001»
14 years 1 months ago
A Layout-Aware Synthesis Methodology for RF Circuits
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
Peter J. Vancorenland, Geert Van der Plas, Michiel...
DAC
2004
ACM
13 years 10 months ago
Fast and accurate parasitic capacitance models for layout-aware
Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tabl...
Anuradha Agarwal, Hemanth Sampath, Veena Yelamanch...
GLVLSI
2003
IEEE
194views VLSI» more  GLVLSI 2003»
13 years 10 months ago
RF CMOS circuit optimizing procedure and synthesis tool
In this paper, we discuss a methodology to design and synthesize analog CMOS components such as RF amplifiers. The inputs of the synthesis tool are the circuit specifications desc...
Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nu...
GECCO
2008
Springer
111views Optimization» more  GECCO 2008»
13 years 5 months ago
Single-objective front optimization: application to rf circuit design
This paper proposes a new algorithm which promotes well distributed non-dominated fronts in the parameters space when a single-objective function is optimized. This algorithm is b...
Eduardo José Solteiro Pires, Luís Me...
DAC
2004
ACM
14 years 5 months ago
ORACLE: optimization with recourse of analog circuits including layout extraction
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...
Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd