49 search results - page 3 / 10 » A Low Power Charge-Recycling CMOS Clock Buffer |
ESSCIRC
2011
12 years 5 months ago
2011
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
ICCAD
1995
IEEE
13 years 9 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
ISLPED
1995
ACM
13 years 9 months ago
1995
ACM
We argue that the clocked-CMOS (C2MOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing market...
ENGL
2007
13 years 5 months ago
2007
—A high driving capability CMOS buffer amplifier with high slew-rate, low power, and low offset voltage for high resolution TFT-LCD source drivers is proposed. Low power and high...