Sciweavers

189 search results - page 2 / 38
» A Low Power Hardware Software Partitioning Approach for Core...
Sort
View
ICCAD
2002
IEEE
82views Hardware» more  ICCAD 2002»
13 years 9 months ago
Hardware/software partitioning of software binaries
Partitioning an embedded system application among a microprocessor and custom hardware has been shown to improve the performance, power or energy of numerous examples. The advent ...
Greg Stitt, Frank Vahid
HIPEAC
2007
Springer
13 years 11 months ago
Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems
Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We combine approaches,...
Major Bhadauria, Sally A. McKee, Karan Singh, Gary...
CISIS
2008
IEEE
13 years 11 months ago
Hardware Software Partitioning Problem in Embedded System Design Using Particle Swarm Optimization Algorithm
Hardware/software partitioning is a crucial problem in embedded system design. In this paper, we provide an alternative approach to solve this problem using Particle Swarm Optimiz...
Alakananda Bhattacharya, Amit Konar, Swagatam Das,...
DAC
2005
ACM
14 years 5 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
13 years 11 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky