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DAC
2005
ACM
14 years 6 months ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo
DATE
2008
IEEE
123views Hardware» more  DATE 2008»
13 years 11 months ago
Test Strategies for Low Power Devices
Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing...
C. P. Ravikumar, M. Hirech, X. Wen
IPCCC
2006
IEEE
13 years 11 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
PDPTA
2000
13 years 6 months ago
On the application of accelerating simulation methods in network analysis
When evaluating quantitative aspects of communication networks using simulation, one of the main difficulties to face is the often considerable computing power required. In some s...
José Incera, Gerardo Rubino, Nicolás...
JSA
2006
113views more  JSA 2006»
13 years 5 months ago
A power-efficient TCAM architecture for network forwarding tables
Stringent memory access and search speed requirements are two of the main bottlenecks in wire speed processing. Most viable search engines are implemented in content addressable m...
Taskin Koçak, Faysal Basci