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ICCAD
2003
IEEE
194views Hardware» more  ICCAD 2003»
14 years 3 months ago
On the Interaction Between Power-Aware FPGA CAD Algorithms
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
Julien Lamoureux, Steven J. E. Wilton
GLVLSI
2010
IEEE
149views VLSI» more  GLVLSI 2010»
13 years 8 months ago
Lightweight runtime control flow analysis for adaptive loop caching
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
Marisha Rawlins, Ann Gordon-Ross
IPPS
2007
IEEE
14 years 18 days ago
C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation
Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have proven to be effective implementation architecture for thes...
Najeem Lawal, Mattias O'Nils, Benny Thörnberg
ERSA
2008
185views Hardware» more  ERSA 2008»
13 years 7 months ago
Design Framework for Partial Run-Time FPGA Reconfiguration
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
Chris Conger, Ann Gordon-Ross, Alan D. George
VLSI
2010
Springer
13 years 29 days ago
A design workflow for dynamically reconfigurable multi-FPGA systems
Multi-FPGA systems (MFS's) represent a promising technology for various applications, such as the implementation of supercomputers and parallel and computational intensive emu...
Alessandro Panella, Marco D. Santambrogio, Frances...