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SBCCI
2005
ACM
115views VLSI» more  SBCCI 2005»
13 years 10 months ago
Design of a decompressor engine on a SPARC processor
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
Richard E. Billo, Rodolfo Azevedo, Guido Araujo, P...
USS
2008
13 years 6 months ago
Practical Symmetric Key Cryptography on Modern Graphics Hardware
Graphics processors are continuing their trend of vastly outperforming CPUs while becoming more general purpose. The latest generation of graphics processors have introduced the a...
Owen Harrison, John Waldron
VLSISP
1998
128views more  VLSISP 1998»
13 years 4 months ago
A Low Power DSP Engine for Wireless Communications
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
Ingrid Verbauwhede, Mihran Touriguian
CODES
2003
IEEE
13 years 9 months ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa
CODES
2004
IEEE
13 years 8 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis