7 search results - page 1 / 2 » A Method for Register Allocation to Loops in Multiple Regist... |
IPPS
1996
IEEE
13 years 9 months ago
1996
IEEE
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
In this paper, we outline general design steps of our synthesis tool to realize application specific co-processors such that for a given scientific application having intensive ite...
ASPLOS
2000
ACM
13 years 9 months ago
2000
ACM
The high arithmetic rates of media processing applications require architectures with tens to hundreds of functional units, multiple register files, and explicit interconnect betw...
PLDI
2005
ACM
13 years 10 months ago
2005
ACM
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
IEEEPACT
2002
IEEE
13 years 9 months ago
2002
IEEE
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...