Sciweavers

789 search results - page 1 / 158
» A Methodology for Accurate Performance Evaluation in Archite...
Sort
View
DAC
2005
ACM
13 years 6 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim
DAC
1999
ACM
14 years 5 months ago
Cycle-Accurate Simulation of Energy Consumption in Embedded Systems
This paper presents a methodology for cycle-accurate simulation of energy dissipation in embedded systems. The ARM Ltd. 1 instruction-level cycle-accurate simulator is extended wi...
Tajana Simunic, Luca Benini, Giovanni De Micheli
DATE
2009
IEEE
150views Hardware» more  DATE 2009»
13 years 11 months ago
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
—Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencie...
Kostas Siozios, Vasilis F. Pavlidis, Dimitrios Sou...
ATAL
1999
Springer
13 years 9 months ago
Toward a Methodology for AI Architecture Evaluation: Comparing Soar and CLIPS
We propose a methodology that can be used to compare and evaluate Artificial Intelligence architectures and is motivated by fundamental properties required by general intelligent ...
Scott A. Wallace, John E. Laird