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ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
14 years 2 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...
JPDC
2006
146views more  JPDC 2006»
13 years 5 months ago
A semi-static approach to mapping dynamic iterative tasks onto heterogeneous computing systems
Minimization of the execution time of an iterative application in a heterogeneous parallel computing environment requires an appropriate mapping scheme for matching and scheduling...
Yu-Kwong Kwok, Anthony A. Maciejewski, Howard Jay ...
ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
13 years 9 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
ICDT
2001
ACM
147views Database» more  ICDT 2001»
13 years 10 months ago
Parallelizing the Data Cube
This paper presents a general methodology for the efficient parallelization of existing data cube construction algorithms. We describe two different partitioning strategies, one f...
Frank K. H. A. Dehne, Todd Eavis, Susanne E. Hambr...
ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
13 years 3 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...