34 search results - page 3 / 7 » A Modular Memory BIST for Optimized Memory Repair |
ITC
2003
IEEE
13 years 11 months ago
2003
IEEE
This paper presents an attempt of using intelligent agents for testing and repairing a distributed system, whose elements may or may not have embedded BIST (Built-In Self-Test) an...
ISQED
2002
IEEE
13 years 11 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
DFT
2003
IEEE
13 years 11 months ago
2003
IEEE
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
CORR
2007
Springer
13 years 6 months ago
2007
Springer
Abstract. Usually, mathematical objects have highly parallel interpretations. In this paper, we consider them as sequential constructors of other objects. In particular, we prove t...
INFORMATICALT
2006
13 years 6 months ago
2006
In this paper optimization of DSR is achieved using New Link Cache structure and Source Transparent Route Maintenance Method. The new link cache effectively utilizes the memory by ...